The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiOx and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with VT (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in VT than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.

► The poly-Si MOSFETs using an ultra-thin HfSiOx has a subthreshold swing of 193 mV/dec.
► It is compatible with monolithic 3D-ICs, SOG, and AMOLED due to thermal budget of 700 °C.
► The fabrication process temperatures and stress reliability were studied.