Characterization and modeling of capacitances in FD-SOI devices

Gate-to-channel capacitance Cgc(Vg) data obtained on FD-SOI MOS devices with gate lengths down to 35 nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure.

► Gate-to-channel capacitance measurements down to 35 nm gate length in FDSOI.
► 2D simulation of parasitic capacitances in FDSOI.
► Discrimination of parasitic capacitances components.