Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20 nm wide fins are fabricated using 193 nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300 nm and the electrically active fin height is 40 nm.

► Bulk Finfets co-fabricated with planar CMOS.
► Non-plasma oxide dry etching introduced to control fin height.
► STI-like approach and CMOS compatibility assured for large scale production.