Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs

In this work, the instability of n-channel 4H–SiC double-implanted metal–oxide–semiconductor field-effect-transistors (DMOSFETs) was studied, in terms of threshold-voltage (VTH) shifts and drain–source current (IDS) transients, for different gate bias stress durations of range 100–5500 s. At room temperature, for positive gate bias stress, the VTH shift and IDS decay increase with increasing stress time. The VTH shift and the IDS decay were recovered by negative gate bias stress. It is believed that the instability in device behavior during positive gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. Elevated temperature measurements have indicated a decrease in VTH and an increase in IDS with increasing stress time possibly due to mobile positive ions in the gate dielectric.