کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
753462 | 895533 | 2007 | 8 صفحه PDF | دانلود رایگان |
Progress in scaling of MOS transistors and integrated circuits over the years is reviewed and today’s status and challenges are described. Generalized scaling is updated for the present leakage-constrained environment to project results of continued scaling at a constant power-supply voltage. Alternatives to achieve energy-efficient operation at lower voltages are discussed. Particular attention is given to threshold variability issues and to the design challenges in reducing and controlling variability using back-gate devices. The importance of the depth of the inversion layer below the silicon surface as a limit to the effectiveness of gate-insulator scaling is illustrated by a design study. Low-temperature operation is considered as a possible future direction for continuing scaling.
Journal: Solid-State Electronics - Volume 51, Issue 4, April 2007, Pages 518–525