Impact of fin width on digital and analog performances of n-FinFETs

This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs (I–V, C–V and 1/f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.