Towards a unified low-field model for carrier mobilities in crystalline silicon

• We present a unified model for carrier mobilities in crystalline silicon.
• Based on Klaassen׳s model we include a correction for compensation.
• The model is valid for majority and minority hole and electron mobilities.
• We extend the correction to the temperature range 80–350 K for majority carriers.
• We suggest a new parameterization for hole scattering at phonons.

The electrical properties of crystalline silicon crucially depend on the mobility of minority and majority charge carriers. As parameters like the conductivity and the diffusion length are directly connected to carrier mobility, its exact prediction is essential for device simulation and material characterization. While generally accepted mobility models exist for uncompensated silicon, strong deviations have been observed in compensated silicon depending on the compensation level. Different approaches have been suggested for modeling majority carrier mobility correcting for compensation. In this work, the controversially discussed physical reasons for mobility reductions in compensated silicon are critically reviewed and we present a unified description of mobility in silicon. Based on the approach suggested by Schindler et al. [Solar Energy Materials and Solar Cells 106 (2012) 31–36], which describes the modeling of majority carrier mobilities in p-type compensated silicon at room temperature, the model is extended to both majority and minority carrier mobilities in p- and n-type compensated silicon at room temperature and a description for the temperature dependence is suggested. Fit parameters are obtained based on a wide range of published and new carrier mobility data presented here. Additionally, a new parameterization for scattering of holes by phonons is presented and included in the model.