Integration of metal insulator metal capacitors (MIM-Caps) with low defectivity into a copper metallization

On-chip integrated MIM capacitors are finding increasing attention for various applications in advanced high-performance mixed signal and RF products. Typical requirements include low area consumption, large specific capacitance, low capacitance tolerances, high quality factors and low parasitic substrate coupling. In this paper, we present an approach for integrating MIM caps into a copper multilevel metallization using Cu lines as bottom electrode for the capacitor. Specific capacitances of 3.5 fF/μm2 with a low overall capacitance spread of less than ±3% have been achieved without violating the stringent reliability, quality and yield requirements of advanced products. The integration scheme allows significantly lower area consumption at equivalent specific capacitance and a two times higher quality factor than the state of the art reference. The major breakthrough in order to use Cu lines with their low serial resistance as bottom electrode was the optimisation of the process flow. Careful engineering of the interfaces between the electrodes and the capacitor dielectric, optimization of several etch and clean processes and fine tuning of the unit processes which are relevant for a smooth Cu surface with low defect counts are described. The final integration flow was leading to a consistently low electrical defect density, which is comparable to the best known values of reference schemes with larger area consumption and lower quality factors.