A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET-MOS hybrid architectures is also reported. The proposed process exploits an original low energy “hot” ion implantation for the doping of the 10 nm ultra-thin nano-grain polysilicon wire that serves for building the single electron transistors. Standard MOSFET characteristics and charge trapping, inducing hysteresis in the IDS-VGS characteristics of the polysilicon wires, are reported.