Strained silicon on insulator (SSOI) by waferbonding

Strained silicon devices provide for an enhanced carrier mobility compared to that of unstrained silicon devices of identical dimensions. The device performance gets even better when using strained silicon on insulator material. We report experimental procedures based on wafer bonding, smart cutting and selective chemical etching to obtain thin strained silicon (∼15 nm) on insulator wafers. The starting material is an 8″ wafer with pseudomorphically grown strained silicon on a so-called virtual substrate as realized by epitaxial chemical vapor deposition of relaxed SiGe (grown with a grading rate of 10% Ge in the SiGe-alloy per 1 μm layer deposition) on a Si(0 0 1) substrate. The starting and bonded wafers are characterized: (i) structurally using transmission electron microscopy, (ii) topographically, using atomic force microscopy and (iii) the strain is quantified using UV-Raman spectroscopy.