Effect of P+ shielding region on single event burnout of 4HSiC trench gate MOSFET

In this work, numerical simulation methods have been applied to a 4HSiC trench-gate MOSFET structure to investigate its susceptibility to single event burnout. With SILVACO ATLAS, the high-k shielded trench-gate MOSFET and high-k trench-gate MOSFET are investigated to prove that P+ shielding region under the trench bottom could provide a leaking path of hole current and improve the device's tolerance to single-event burnout. The simulation results show that the using of P+ shielding region makes the burnout threshold voltage change from 360 V in high-k trench-gate MOSFET to 470 V in high-k shielded trench-gate MOSFET, about 30.6% improvement in the performance of SEB.