کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10364806 | 871824 | 2005 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Substrate interconnect technologies for 3-D MEMS packaging
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronic Engineering - Volume 81, Issue 1, July 2005, Pages 106-116
Journal: Microelectronic Engineering - Volume 81, Issue 1, July 2005, Pages 106-116
نویسندگان
Brian Morgan, Xuefeng Hua, Tomohiro Iguchi, Taizo Tomioka, Gottlieb S. Oehrlein, Reza Ghodssi,