Scaling CMOS: Finding the gate stack with the lowest leakage current

In order to reduce the gate leakage current, high-k gate dielectrics are expected to replace SiO2 in future CMOS generations. Many of these novel dielectrics are stacks of a thin SiO2 and a high-k layer. We present a theoretical study that aims at identifying the combination of the stack architecture and high-k material with the lowest leakage current. In the first part of this work the leakage current through high-k double stacks with various thicknesses, materials and gate electrodes is calculated assuming tunneling only. We discuss the difference between gate and substrate injection and show quantitatively the impact of interfacial layer thickness, barrier height, k-value and the work function of the gate material on the tunneling current. In the second part the material properties are no longer considered to be independent and with the universal relation between k-value and barrier height introduced, we are able to identify what material suits best all requirements. The leakage current is calculated for different EOTs and we demonstrate that if all dielectrics follow this universal relation, for a fixed thickness there exists one material, which gives a minimum gate leakage current. It is concluded that even for sub 1 nm EOT devices the k-value has not to exceed ∼25 and ZrO2 or HfO2 come closest to the ideal high-k if only leakage current issues are considered.