کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
10411209 | 894558 | 2005 | 4 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی برق و الکترونیک
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چکیده انگلیسی
A physical, compact, short-channel threshold voltage model for undoped double-gate MOSFETs has been extended through a phenomenological approach to include the fringe-induced barrier lowering (FIBL) effect associated with high-permittivity (high-k) gate dielectrics. The resulting analytical model closely describes published numerical simulations over a wide range of device/material parameters. Exploiting the new device model, a concerted analysis combining FIBL-enhanced short-channel effects and gate direct tunneling current is performed on candidate high-k gate dielectrics to assess their overall impact on DG MOSFET scaling. It is projected that high-k gate dielectrics may extend DG MOSFET scaling beyond that with SiO2 by 10-20% for a 2-3Ã smaller equivalent oxide thickness of high-k dielectrics than that of SiO2.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 49, Issue 2, February 2005, Pages 271-274
Journal: Solid-State Electronics - Volume 49, Issue 2, February 2005, Pages 271-274
نویسندگان
Qiang Chen, Lihui Wang, James D. Meindl,