کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
11020905 1715047 2018 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
On-chip implementation of a low-latency bit-accurate reciprocal square root unit
ترجمه فارسی عنوان
پیاده سازی یک چیپ یک واحد ریشه مربعی تقریبا دقیق باقیمانده کمی
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
چکیده انگلیسی
Many applications such as gaming, digital signal processing and communications systems, require computation of the reciprocal square root operation (RSR). Although several architectures have been reported for computing the RSR operation, these are mainly focused on accelerating high-precision floating-point units. In mobile-device implementations, fixed-point (FxP) units are preferred due to their low computational cost and power consumption. This article presents an on-chip implementation of a bit-accurate, FxP-RSR unit using a 130 nm CMOS process. The proposed architecture is based on a piecewise-polynomial approximation in a reduced range of the RSR function and the Newton-Raphson method. Experimental results show that the manufactured chip exhibits lower latency and less power consumption than existing standard-cell-based implementations. These characteristics make the proposed chip a useful silicon intellectual property suitable for embedded applications where low power, low latency, and low hardware cost is required.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration - Volume 63, September 2018, Pages 9-17
نویسندگان
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