A low-power cryogenic analog to digital converter in standard CMOS technology

• A MOS device model for circuit simulation at cryogenic temperatures is designed.
• The proposed ADC can function from room temperature down to 20 K.
• A integral-based comparator is used to eliminate the impact of freeze-out.
• The proposed circuit has the advantages of low power, high speed and resolution.

This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) in standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology that functions from 300 K (room temperature) down to 20 K. It has been designed to operate in low temperature mid- and far-infrared imaging systems. In order to ensure the circuit performance at the extreme temperatures, a dedicated integral-based comparator architecture is employed. SPICE models have been developed for circuit simulation at 20 K. At 20 K, the experimental results exhibit that the ADC achieves 1.6 LSB maximum differential nonlinearity (DNL), 1.7 LSB maximum integral nonlinearity (INL), and 10.4 effective number of bits (ENOB) at 100 kS/s sampling rate with a current consumption of 75 μA from a 3.3 V supply.