Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform

• InAs based doping-less Tunnel FET is proposed and investigated.
• The impact of gate stacking (SiO2 + HfO2) is discussed for various analog/RF parameters.
• Eliminates the fabrication issues such as uniform doping and thermal budget.
• Provides enhanced performance compared to doped device.

In this paper for the first time, InAs based doping-less Tunnel FET is proposed and investigated. This paper also demonstrates and discusses the impact of gate stacking (SiO2 + HfO2) with equivalent oxide thickness EOT = 0.8 for analog/RF performance. The charge plasma technique is used to form source/drain region on an intrinsic InAs body by selecting proper work function of metal electrode. The paper compares different combinations of gate stacking (SiO2 and HfO2) on the basis of different analog and RF parameters such as transconductance (gm), transconductance to drive current ratio (gm/ID), output conductance (gd), intrinsic gain (AV), total gate capacitance (Cgg) and unity-gain cutoff frequency (fT). The proposed device produces an ON state current of ION ∼6 mA along with ION/IOFF ∼1012, point subthreshold slope (SS ∼ 1.9 mV/dec), average subthreshold slope (AV-SS ∼ 14.2 mV/dec) and cut-off frequency in Terahertz. The focus of this work is to eliminate the fabrication issues and providing the enhanced performance compared to doped device.