Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

• Impact of different High-k spacer materials on Gate Stack U-DG-NMOSFET.
• Subthreshold Analog/RF Performance for different spacer materials on Gate Stack U-DG-NMOSFET.
• Extraction of AC small signal parameters for different spacer materials on Gate Stack U-DG-NMOSFET.
• RF parameters extraction using the Non Quasi Static (NQS) model of the U-DG-GS NMOSFET.
• Single stage amplifier analysis of the Gate Stack U-DG-NMOSFET with different spacer materials.

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE’s), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.