Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation

• A novel Fe SB-TFET with gate-drain underlap is proposed and investigated.
• The Fe SB-TFET uses ferroelectric gate stack in place of conventional SiO2.
• 2D device simulation is used to investigate the DC performance of the device.
• The Fe SB-TFET achieves improved performance than the conventional SB-TFET.
• Using gate-drain underlap, ambipolar leakage current is effectively suppressed.

In this paper, for the first time, a novel ferroelectric schottky barrier tunnel FET (Fe SB-TFET) is proposed and investigated. The Fe SB-TFET consists of ferroelectric gate stack with highly doped pocket at the source/drain and channel interface. In addition, for the suppression of ambipolar leakage current (IAMB), gate-drain underlap is employed. By using ferroelectric gate stack, we effectively amplified the applied gate voltage to enhance electric field for the reduction of tunneling barrier width at the source side schottky barrier. As a result, the increased tunneling probability improves the device performance in terms of high ION, high ION/IOFF ratio, reduced IAMB and low subthreshold swing (SS) as compared to the conventional SB-TFET having double pocket. We also investigate the influence of highly doped pocket (HDP) doping concentration and length on the device performance.