The influence of gate underlap on analog and RF performance of III-V heterostructure double gate MOSFET

In recent times, InP/InGaAs heterostructure double gate (DG) MOSFET emerges as one of the promising contender for future generation n-MOSFETs design based on its augmented electron mobility. In this work, we have analyzed the influence of gate underlap on the analog and RF performance of InP/InGaAs hetero-junction FET using TCAD device simulation. A comprehensive and quantitative analysis of the key analog and RF figure-of-merits such as drain resistance (RDS), transconductance (gm), cutoff frequency (fT) and maximum frequency of oscillation (fmax) are performed for various underlap length ranging from 2 nm to 9 nm. Simulation reveals that the analog and RF performance of heterostructure DG MOSFET is severely affected by the amount of underlap length. A trade-off between the analog and RF performance is observed, which can be controlled by a judicious selection of the underlap length.