TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation

Part I of this paper dealt with the hot carrier reliability evaluation of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET involving channel recession and gate electrode workfunction engineering integration onto the conventional MOSFET, using an ATLAS device simulator. It was demonstrated that with the gate stack architecture incorporated onto the GEWE-RC MOSFET and tuning of various structural design parameters such as gate length (LGLG), negative junction depth (NJD), substrate doping (NANA), gate metal workfunction, substrate bias (VSUBVSUB), drain bias (VDSVDS) and gate oxide permittivity (εox2εox2), excellent hot carrier immunity can be achieved in terms of conduction band offset, reduced electron velocity, electron temperature, hot electron injected gate current and impact ionization substrate current. This paper focuses on the analog and large signal performance metrics in terms of linearity, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design parameters such as LGLG, NJD, NANA, gate metal workfunction and εox2εox2 for different substrate (VSUBVSUB) and drain to source (VDSVDS) voltages. The work, thus, proves the effectiveness of GEWE-RC for RFICs with a higher efficiency, better linearity performance; and designing and modeling of power amplifiers.