Large area SiC substrates and epitaxial layers for high power semiconductor devices — An industrial perspective

We review the progress in the industrial production of SiC substrates and epitaxial layers for high power semiconductor devices. Optimization of SiC bulk growth by the sublimation method has resulted in the commercial release of 100 mm nn-type 4H-SiC wafers and the demonstration of micropipe densities as low as 0.7 cm−2 over a full 100 mm diameter. Modelling results link the formation of basal plane dislocations in SiC crystals to thermoelastic stress during growth. A warm-wall planetary SiC-VPE reactor has been optimized up to a 8×100 mm configuration for the growth of uniform 0.01–80-micron thick, specular, device-quality SiC epitaxial layers with low background doping concentrations of <1×1014 cm−3, and intentional pp- and nn-type doping from ∼1×1015 to >1×1019 cm−3. We address the observed degradation of the forward characteristics of bipolar SiC PiN diodes [H. Lendenmann, F. Dahlquist, J.P. Bergmann, H. Bleichner, C. Hallin, Mater. Sci. Forum 389–393 (2002) 1259], and discuss the underlying mechanism due to stacking fault formation in the epitaxial layers. A process for the growth of the epitaxial layers with a basal plane dislocation density <10 cm−2 is demonstrated to eliminate the formation of these stacking faults during device operation [J.J. Sumakeris, M. Das, H.McD. Hobgood, S.G. Müller, M.J. Paisley, S. Ha, M. Skowronski, J.W. Palmour, C.H. Carter Jr., Mater. Sci. Forum 457–460 (2004) 1113].