GaP-nucleation on exact Si (0 0 1) substrates for III/V device integration

This paper summarizes our present knowledge of the defect-free nucleation of III/V semiconductors on exactly oriented Si (0 0 1) surfaces. A defect-free III/V nucleation layer on Si (0 0 1) substrates is important for integrating optoelectronic functions on Si substrates, like III/V-based lasers and solar cells as well as high-mobility III/V-n-channel layers. For applications which rely on CMOS processing and devices, one should choose (0 0 1) Si substrates with no intentional off-cut (exactly oriented ±0.5°). Under high hydrogen pressures and at high annealing temperature, one can maximize the number of double steps even on this Si surface under vapour phase epitaxy (VPE) conditions. A GaP layer free from dislocations, stacking faults, twins and/or antiphase disorder can be grown on a Si homoepitaxial buffer by metal organic vapour phase epitaxy (MOVPE) in a two step process. We show that a thin and low temperature GaP nucleation layer has to be deposited in flow rate modulated growth mode to achieve a charge neutral interface and two-dimensional growth. A GaP layer grown at high temperature on this nucleation layer results in self-annihilation of the remaining antiphase domains. This defect-free GaP layer with a total thickness of only about 50 nm can serve as a template for subsequent integration of III/V device structures on Si (0 0 1) substrates.