C2FPGA—A dependency-timing graph design methodology

In this paper, we present a design methodology that uses a combined graphical and scheduling technique to map C-based high level language (HLL) based applications to FPGA. Although there are a number of approaches addressing the mapping from HLL to hardware, many of these existing solutions either require a steep learning curve or do not produce an appropriate mapping pattern for the hardware platform. We provide a solution to this problem, by analyzing the data flow and data dependencies in the given code and proposing a scheduling patterns for the given algorithm. We then provide a suitable mapping pattern for the hardware platform. We use the mapping pattern to deliver synthesizable HDL (Verilog) code. We demonstrate our design methodology with results from different real-time case studies that are based on different algorithms.

► Different algorithms to optimally schedule tasks on an FPGA are explored.
► A high-level tool is developed to map applications to FPGA.
► Important hardware concept of FPGAs, i.e. clock is addressed.
► DDG is generated and the design space is explored.
► Better speedup is achieved compared to a manual design.