Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric

Tunneling field-effect transistors (TFETs) are gaining attention because of their good scalability and low leakage current. However, they suffer from low on-state current and severe ambipolar conductivity. To address these issues, in this paper, we have proposed a novel junctionless nanowire TFET with induced source side tunneling realized by a hetero-gate-dielectric (HGD JN-TFET). This approach induces a local dip in the conduction band edge at the tunneling junction leading to an abrupt transition between the on and off-states as well as subthreshold swing (SS) as low as 45 mV/dec at low drain voltages. The proposed structure provides Ion of 8.7×10−6 A/µm and Ioff of 1.1×10−11 A/µm. Also, we have shown that the length of high-k gate insulator as well as its dielectric constant can significantly affect the performance and power efficiency of this device.