Synergistic combinations of dielectrics and metallization process technology to achieve 22 nm interconnect performance targets

An improvement in interconnect performance implies a reduction of the resistance–capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22 nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.

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