Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell

FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32 nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22 nm node 6T-SRAM cell. Key in this work was achieving the required CD and profile target specs for the fin and the gate level. Also, the implant levels, though still a 450 nm pitch, turned out to be more difficult than expected because of the underlying topography. All this work resulted in the first electrically functional 22 nm node SRAM cell, with the contact and metal level exposed on the ASML EUV α-demo tool.