Fluid–structure interaction analysis on the effect of chip stacking in a 3D integrated circuit package with through-silicon vias during plastic encapsulation

• An experiment was carried out to validate the numerical studies.
• A total of four models with through-silicon vias were studied numerically.
• A constant ratio of inlet and outlet gate heights was applied.
• Unfavorable deformation is anticipated when more stacked chips are employed.

This paper presents the effect of chip stacking in a 3D integrated circuit package during plastic encapsulation. An experiment was conducted on four stacked chips with bumps in a perimeter array. The flow front advancement and chip displacement in the experiment were validated by using FLUENT 6.3 and ABAQUS 6.9, respectively. A total of four models, which consist of two, three, four, and five stacked chips with through-silicon vias, were studied numerically. A simultaneous or direct solution procedure was employed to solve the variables of the fluid/structural domain. This approach provides better visualization of the actual plastic encapsulation process by considering the fluid–structure interaction phenomenon during the process. A constant ratio of inlet and outlet gate heights was applied to create a more uniform flow front advancement among the models. Results indicate that the highest displacement occurred in Model 4, which contains the most stacked chips. The highest von Mises stress was also detected in Model 4. Therefore, unfavorable deformation is anticipated when more stacked chips are employed. The experimental and numerical studies provide useful information in understanding the fluid flow of epoxy resin and subsequent structural deformation under the effect of chip stacking.

The figure shows the FSI implications to chip deformation during plastic encapsulation. The initial and final chip deformation is displayed.Figure optionsDownload as PowerPoint slide