Reliability of copper low-k interconnects

For the implementation of copper and low-k materials into a tight pitch damascene interconnect architecture it is important to understand and correctly describe the underlying degradation mechanisms during reliability testing. Based on the understanding solutions can be proposed for avoiding fast degradation. While the physical understanding of electromigration mechanisms is less of a debate, technological challenges towards the fabrication of metal wires/vias able to carry the ever increasing current densities are enormous. Recently a number of novel metallization schemes including ruthenium and its alloys or self-forming barriers were proposed. As a consequence, some of the thermodynamic and kinetic behavior of the system can be modified when compared to the conventional Ta-based metallization. Another important component of the system is the insulating low-k dielectric. When scaling the critical dimensions into 50 nm ½ pitch and beyond, the impact of layout and line edge roughness becomes important. If a double patterning approach is used for printing a tight metal pitch, then misalignment between the different photos will exacerbate the layout induced effects. The choice of dielectric material, test structure design and damascene process steps will contribute on top of these effects. Based on recent understanding we review some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint.