Charge transport in high-κ stacks for charge-trapping memory applications: A modeling perspective (invited)

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining their similarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-κ stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-κ tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.

In this paper, we review the most important physics-based models proposed in the literature to reproduce the electrical behavior of charge trapping memory devices. Such models link the electrical behavior of the device under typical operating conditions to its geometry and the physical properties of the materials, thus constituting a basic tool for the understanding of the physical mechanisms governing the device operation and reliability. We show that the use of these models allows gaining important insights into the mechanisms governing the reliability of advanced TANOS devices, typically related to the material defectiveness of alumina blocking layer and band-gap engineered tunnel dielectric stacks.Figure optionsDownload as PowerPoint slideHighlights
► Charge trapping (CT) memories could be a promising technology for further NAND Flash scaling.
► Physics-based models are crucial to understand the physics governing CT device operation and reliability.
► In this paper we review the basic features of the models proposed for CT memory devices.
► We present also a physical model of the charge transport in high-k stacks, which allows explaining reliability issues of advanced CT devices.
► This allows assessing the scalability limits and ultimate performances of the CT memory technology.