کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
540491 | 871316 | 2011 | 4 صفحه PDF | دانلود رایگان |
The electrical characterization of unprocessed fully depleted silicon-on-insulator (SOI) layers relies on the pseudo-MOSFET (Ψ-MOSFET) technique. We propose three-interface models which are more appropriate for addressing the case of SOI wafers with ultrathin body and BOX (UTB2). The novel models for threshold voltage and subthreshold swing account for the channel-to-surface and channel-to-substrate coupling which are important effects, respectively, in ultrathin films and thin BOX. The influence of the density of traps at each of the three interfaces (free surface, channel/BOX and BOX/substrate) is discussed. The models are validated with experimental results from a range of SOI film thicknesses.
The electrical characterization of unprocessed fully depleted Silicon-on-Insulator (SOI) layers relies on the Pseudo-MOSFET (Ψ-MOSFET) technique. We propose 3-interface models which are more appropriate for addressing the case of SOI wafers with ultrathin body and BOX (UTB2). The novel models for threshold voltage and subthreshold swing account for the channel-to-surface and channel-to-substrate coupling which are important effects, respectively in ultrathin films and thin BOX. The influence of the density of traps at each of the three interfaces (free surface, channel/BOX and BOX/substrate) is discussed. The models are validated with experimental results from a range of SOI film thicknesses.Figure optionsDownload as PowerPoint slideResearch highlights
► We propose three-interface models appropriate for addressing the case of SOI wafers with ultrathin body and BOX.
► The novel models for threshold voltage and subthreshold swing account for the channel-to-surface and channel-to-substrate coupling.
► The influence of the density of traps at each of the three interfaces (free surface, channel/BOX and BOX/substrate) is discussed.
► The models are validated with experimental results.
Journal: Microelectronic Engineering - Volume 88, Issue 7, July 2011, Pages 1236–1239