Negative-gate to substrate erase transient simulation for flash memory

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson’s equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process.