RF characterization of the substrate coupling noise between TSV and active devices in 3D integrated circuits

• Innovative and realistic 4-port test structures for high wide frequency range characterizations.
• Extraction of noise coupling between TSVs and wells in a CMOS 65 nm technology node up to 40 GHz.
• Variations in TSV to MOS-wells coupling factors according to polarization is due to p-n junctions.
• Physical model built to explain the changes in coupling factor.
• Comparison of sensitivity of MOS wells to coupling with TSV.

3D technology (TSVs, RDL, copper pillars) is gaining more and more interest. The functionalities and performances of the Wide I/O prototype (memory on logic 3D IC), developed by ST, ST-Ericson and CEA-LETI, was fully demonstrated. 3D process is mature enough to address next applications such as radiofrequency, analogic, and photonics. Nevertheless new challenges appear when 3D technology and these applications meet together. Particularly the parasitic electrical coupling of the TSV with active devices is a matter of interest and is investigated in this paper.Considering that the TSV will be a connection for several applications, characterized by a wide frequency domain, the signal transmission could generate substrate noise impacting MOS circuit operations. Noise coupling between TSV and active areas has to be characterized on a wide frequency range. The extraction of this coupling factor in the complex 3D circuit environment represents the bigger challenge of this study.An original strategy is proposed to investigate the coupling between TSVs and the complex MOS structure, consisting in splitting up the MOS into elementary wells with adequate doping conditions. It entailed innovative test structure design and definition of characterization method with RF and DC sources. The TSV under test is near different MOS wells and the noise coupling transfer factors were measured from 10 MHz to 40 GHz. They exhibit wide variations, increasing with frequency, from minimum −55 dB to maximum −25 dB. Variations according to the well implant and its applied polarization is also observed. It is explained by the presence of p-n junctions which is in agreement with an equivalent electrical model of structure.The sensitivity to substrate noise of PMOS and NMOS wells, standing for drain, source and bulk plug, were characterized and compared. TSV coupling with PMOS device is expected to be more critical than with NMOS. P+ plug is shown to be an efficient solution for substrate noise reduction.

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