Relevance of the pulsed capacitance–voltage measurement technique for the optimization of SrBi2Ta2O9/high-k stack combination to be used in FeFET devices

The ferroelectric field effect transistor (FeFET) with metal–ferroelectric–insulator–semiconductor (MFIS) structure has attracted a lot of interest recently as a nonvolatile memory device. For best performances of FeFET with ferroelectric/high-k gate stacks, the deposition techniques as well as the materials for both the ferroelectric layer and the high-k buffer layer must be carefully selected. In this work, 120 nm SrBi2Ta2O9 (SBT) films were deposited on Al2O3 or HfO2 buffer layers by metal organic chemical vapor deposition (MOCVD) or metal organic decomposition (MOD) techniques. The different SBT/high-k stack combinations were optimized considering not only the remnant polarization of the SBT film, extracted from high-frequency capacitance–voltage (CV) measurements, but also considering the electron trapping–detrapping delay accessed by pulsed CV measurements, which gives insight into the electrical response to very fast program and read pulses. Based on these criteria, the MOCVD SBT/HfO2 gate stack was found to be the best choice, resulting in a memory window of 0.45 V measured for a gate voltage scan range of only ±5 V. The memory switching occurs at rather low voltage due to the use of thinner SBT than typically reported. This optimized stack combination also exhibited low electron trap density and low leakage.