Double gate dielectric stacks with Gd2O3 layer for application in NVSM devices

• Experimental results promising for the application of Gd2O3 in NVSM devices.
• Electro-physical parameters are in accordance to low voltage memory devices demands.
• Better retention time of UFB in comparison stacks with ALD high-k has been observed.
• MISFETs’ wide memory window extrapolated at ten years was obtained.

This work presents the feasibility study of application of gadolinium trioxide (Gd2O3) layers in double-gate dielectrics stacks for non-volatile semiconductor memories (NVSM). In the course of this work metal–insulator–semiconductors (MIS) structures with SiO2/Gd2O3 stacks have been fabricated and characterised by means of current–voltage (I–V) and split-CV techniques. Moreover, memory characteristics were investigated and compared to MIS structures with stacks based on atomic layer deposited (ALD) hafnium dioxide (HfO2) and aluminum trioxide (Al2O3) layers. Presented results have shown low leakage current density of fabricated SiO2/Gd2O3 of the order of 10−6 A/cm2 at 5 MV/cm of equivalent electric field intensity, low interface trap density (Nit) ∼2 × 1011 cm−2 and moderate mobility of MISFETs with studied stacks in the range of 140–380 cm2 V−1 s−1. Moreover, the decrease of retention time extrapolated at ten years of the order of 12% was determined which is significantly lower in comparison to MIS stacks with ALD high-k dielectric layers. In the case of MISFET’s threshold voltage (Ut) relatively broad memory window has been obtained around 1.67 V which makes the investigated double-gate dielectric stack as the potential candidate for low voltage memory applications.

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