Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications

• It was shown that junctionless NW tunnel FET has presented tremendous potential as it combines advantage of JLFET, which has relatively high ON-current and TFET, which has low subthreshold.
• Junctionless tunnel FET is appropriate for low-operating-voltage application.
• The change of bandgap is one of the effects of applying uniaxial tensile strain on NWs.
• Then, the effect of uniaxial tensile strain on electrical performance of these FETs are investigated.
• We show that strain can significantly improve the amounts of ON-current and analogue parameters.

In this paper, we investigated gate-all-around silicon nanowire (NW)-based junctionless tunnel field effect transistor (FET) which is called junctionless tunnel NWFET (JL-TNWFET) with the impact of variation of amount of uniaxial tensile strain on band-to-band tunneling (BTBT) injection and electrical characteristics. The tunneling model is first calculated for measurements of gate-controlled BTBT in the JL-TNWFET and is compared with the strained JL-TNWFET with similar technology parameters. The simulation results show that the JL-TNWFET have potential for low-operating-voltage application (Vdd $_amp_$lt; 0.4 V) and represent high ION/IOFF ratio and steep subthreshold swing over many decade while encompassing high ON-state currents. Whereas, the strained JL-TNWFET due to thinner tunneling barrier at the source-channel junction which leads to the increase of carrier tunneling rate shows excellent characteristics with high ON-current, superior transconductance (gm) and cut-off frequency (ƒT).

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