Study of etching bias modeling and correction strategies for compensation of patterning process effects

• A promising correction strategy is proposed for simultaneous compensation of lithography and etching process effects.
• In order to conduct this study, an etching bias modeling method is investigated by rigorous process simulations.
• The resulting model can simulate etching process effects reasonably well.
• The correction accuracy obtained is significantly improved compared with that obtained by the staged correction strategy.
• The total run time required is increased by a factor of ∼2.5, which is practically acceptable for full-chip correction.

In addition to simulating lithography process effects, process models must accommodate pattern distortion due to the etching process. An etching bias modeling method and a staged correction strategy have been developed to compensate for such patterning process effects efficiently. However, the staged correction strategy may cause inaccurate compensation of patterning process effects since the patterns used to simulate etching process effects are assumed to be rectilinear. In fact, the patterns will be distorted during the lithography process. Therefore, a promising correction strategy that incorporates a recently developed optical proximity correction algorithm is proposed to deal with this problem. It can compensate for lithography and etching process effects simultaneously. In order to conduct this study, the etching bias modeling method is investigated by rigorous process simulations. The resulting model provides a reasonable fit to the measured data from the process simulations and can simulate etching process effects reasonably well. The performance of the proposed correction strategy in terms of correction accuracy and run time is examined. Numerical experiments show that the correction accuracy obtained is significantly improved compared with that obtained by the staged correction strategy. However, the total run time required is increased by a factor of ∼2.5, which is practically acceptable for full-chip correction.

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