Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm Si cores on bulk Si using 0.8 μm optical lithography and local oxidation for the first time. 0.833 GPa uniaxial tensile stress is measured in the buckled suspended dual Si nanowires using micro-Raman spectroscopy. The array of GAA buckled dual Si nanowire MOSFETs at VDS = 50 mV shows 64 mV/dec. subthreshold slope and 61% stress-based low-field electron mobility enhancement in comparison to the omega-gate relaxed reference device. Finally, digital logic implementation is demonstrated using multi-gate nanowires on bulk Si.

Fabrication of buckled dual Si nanowires with sub-80 nm cross-sections using 0.8 m optical lithography and local oxidation on bulk Si substrate.Figure optionsDownload as PowerPoint slideHighlights
► Formation of GAA buckled suspended dual NWs on bulk Si using 0.8 μm lithography.
► NW cross-section shrinkage down to 80 nm by local oxidation.
► Stress measurement on buckled dual NWs by micro-Raman spectroscopy.
► Stress-based carrier mobility enhancement report in the GAA buckled dual NWs.
► Low voltage digital logic implementation using multi-gate nanowires on bulk Si.