“Smart” TDDB algorithm for investigating degradation in high-κ gate dielectric stacks under constant voltage stress

A new “smart” algorithm with adaptive testing is developed for automatically monitoring gate dielectric degradation during CVS using SILC. In this approach, stress current is monitored with a sampling rate as fast as ∼2 ms/point while SILC data are collected based on stress current changes and/or time intervals. This automated test was applied to study degradation of nMOS transistors with TiN/HfO2 gate stacks where changes in the SILC data correlate directly with transitions in the stress current. From this SILC data, the differential resistance can be extracted and used to monitor conductivity throughout the degradation phase until breakdown.