کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
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545129 | 871809 | 2007 | 5 صفحه PDF | دانلود رایگان |
Ceria-based high selectivity slurry (HSS), which shows high polishing selectivity of silicon oxide to silicon nitride, was applied to the shallow trench isolation (STI) chemical mechanical planarization (CMP) process for giga-bit scale memory fabrication. While the wafer-to-wafer non-uniformity (WTWNU) and within-wafer non-uniformity (WIWNU) are superior to conventional silica-based slurry, the level of slurry induced scratches is too high for the ceria-based slurry to be used in present CMP processes. By optimizing the CMP process and filtering method, however, the number and depth of these scratches were reduced considerably to the level where the yield of gate oxide was sufficient to meet the requirement of manufacturing. In this paper, the authors discussed the possible causes of scratches when using ceria-based slurry and how these scratches affect to lower the breakdown yield of gate oxides. In addition, the authors investigated the relationship between within wafer non-uniformity and cell threshold voltage (Vt) variation and probe test 1 (PT1) yield variation.
Journal: Microelectronic Engineering - Volume 84, Issue 4, April 2007, Pages 626–630