Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, tox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage Vth and of linear drain current Idlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of Vth and Idlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO2/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.