Design of stable parallel feedforward compensator and its application to synchronization problem

This paper addresses the design problem of a stable parallel feedforward compensator V for a given SISO LTI plant P (possibly being of non-minimum phase and/or having relative degree greater than one). The objective of the problem is that their parallel interconnection P+V becomes minimum phase having relative degree one. Based on the classical results of simultaneous stabilization, a necessary and sufficient condition for solving the problem is presented as well as a design procedure for constructing such a compensator. The proposed feedforward compensator allows the control system to have the three useful features: (1) the ability that assigns the zeros of P+V to a region of complex numbers having arbitrary negative real parts, (2) infinite gain margin property of P+V controlled by a static output feedback, and (3) block diagonal structure of P+V. These features are extensively exploited in the synchronization problem of multi-agent systems to achieve arbitrary fast convergence rate and to have the synchronized trajectory independent of the initial conditions and parameters of the involved dynamic controllers.