Anisotropic equivalent thermal conductivity model for efficient and accurate full-chip-scale numerical simulation of 3D stacked IC

The complexity of thermal management increases as integrated circuits evolved into 3D architectures. Because of the large variation that exists in the thermal conductivity of materials and the geometrical size of structures in the 3D-stacked IC (3D-SIC) network, the extensive computational costs typically render a full-chip-scale numerical simulation impossible. Thus, this paper proposes a fast and implementable full-chip-scale numerical simulation method for thermal management of 3D-SIC. A compact thermal resistance network, with both lateral and vertical heat dissipations considered, is analyzed to establish an accurate anisotropic equivalent thermal conductivity model. The key heat dissipation component, the high thermal conduction path (HTCP) constructed using through-silicon vias (TSVs), micro-bumps, and Cu wires in the redistribution layer (RDL), is fully analyzed by modeling a compact thermal resistance network. The equivalent thermal conductivity of each stacked layer is extracted in blocks from the network and then applied in a finite element calculation for full-chip-scale numerical simulation. Three partitioning strategies to block each stacked layer are tested. As compared to the results of direct finite element simulation of a small-scale 3D-SIC, the proposed method yields improved simulation accuracy (temperature difference <7.5%) and a considerable computational cost reduction (grid number reduced by >77%). As a demonstration, the temperature distribution of a large-scale 3D-SIC with 306 TSVs and 1647 hotspots is successfully simulated within 82 min by implementing this method using a personal computer (Intel Core i5 6300HQ, 60 GB memory).