Impact of germanium surface passivation on the leakage current of shallow planar p–n junctions

One of the challenges in the development of CMOS on Ge is the fabrication of low-leakage shallow junctions. Like in the case of silicon technology, one aims to achieve this goal by ion-implantation of the dopants followed by a thermal activation step. The thermal budget should be low enough to minimize excessive diffusion but at the same time sufficient to remove the lattice damage and activate the dopants. However, as will be shown, for the planar junctions fabricated in germanium substrates, another factor dominates the leakage current, namely the surface generation current in the peripheral regions surrounding the diode. This emphasizes the role of adequate surface passivation. Results will be presented for diodes fabricated in 100 mm diameter p- and n-type Ge wafers, using different dielectrics as surface passivation layer, namely 20 nm Si3N4 deposited by CVD and GeON/HfO2 (4 nm) deposited by MBE. A difference of up to five decades between forward and reverse current has been achieved. Analysis of the area/perimeter scaling of the reverse current demonstrates that even for these junctions, the surface generation current is dominant. It will also be pointed out that the substrate doping density plays an important role.