Low power, GHz class ADC for broadband applications

The design of ultra-low power (<100 mW), high-speed analogue to digital converter (ADC) is an essential element for the next generation radio telescope, the square kilometre array (SKA). CMOS technology is limited in high precision applications, such as ADCs due to the stringent requirement of device matching. Also to achieve high-speed (ft>100 GHz) CMOS requires deep sub-micron gates (90 nm or less) where expensive phase shift masks are required. This paper describes the design and simulation of a low-power high-speed (4 GS/s) analogue to digital converter based on an InP/InGaAs heterojunction bipolar transistor (HBT). The technology used was developed at the University of Manchester using MBE growth which relied upon two novel developments. Firstly stoichiometric conditions permitted growth at a fairly low temperature of 420 °C while conserving extremely high-quality materials. Secondly dimeric phosphorus was generated from a gallium phosphide (GaP) decomposition source leading to excellent RF device properties. The DC and RF performance of the fabricated HBTs showed characteristics ideally suited to low-power IC designs, with current gain ∼70, low offset voltages and achieving an ft=91 GHz and fmax=83 GHz on a 1.5×5 μm2 emitter area device using fairly relaxed optical lithography.