Electrothermal simulation of SOI CMOS analog integrated circuits

An analytical approach, combining a heat flow device model for SOI devices and a thermal model for interconnects, is presented for electrothermal simulation of SOI analog integrated circuits. The proposed approach is able to account for large temperature gradients in device, heat exchanges between devices, heat losses from the silicon islands and interconnects to the substrate through oxide, and temperature influences on electronic characteristics. Electrothermal simulations of SOI analog integrated circuits in SPICE coupled with the proposed approach are performed and compared with the isothermal model using the BSIMSOI thermal circuit. Heat flow, thermal coupling and self-heating effects in some SOI analog integrated circuits influenced by non-isothermal effects are examined. Limitations of the BSIMSOI isothermal is discussed.