The impact of stress-induced defects on MOS electrostatics and short-channel effects

• Development of compact model for SCE that incorporates stress-induced defects.
• Model captures the impact of Dit and Not on MOS electrostatics and DIBL.
• The presented model is physics-based and uses calculations of surface potential.
• Model calculations are verified with TCAD simulations and experimentally.
• Relates MOS electrostatics and characteristic scaling length with MOS reliability.

This paper investigates the influence of stress-induced oxide-trapped charge and interface traps on the electrostatics of metal–oxide–semiconductor (MOS) devices and its relation to short-channel effects (SCE). Interface trap and oxide-trapped charge densities are included in the derivation of scaling models that are based on solving Poisson’s equation in the depletion approximation (i.e., in weak inversion) using analytical approximations for the electrostatic potential. The impact of interface traps and oxide-trapped charge on the electrostatic potential profile, scaling, and short-channel effects are modeled analytically and verified with TCAD simulations. The theory and modeling approach is validated through comparisons with the experimental extraction of SCE in n-channel MOS field-effect transistors (MOSFETs) measured before and after hot-carrier stress.