Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

• We developed a novel method of crystallization of amorphous silicon films.
• We report a few methods for preventing arc generation in this article.
• We devised the method of producing the JIC poly-Si TFTs.
• We fabricated coplanar top-gate poly-Si TFTs without redundant processing steps.
• Short time electrical pulsing ensured sharp interfaces in PMOS JIC poly-Si TFTs.

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.