Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology

• Selective growth of B-doped SiGe layers on trapezoidal FinFETs of 14 nm node.
• The epitaxial quality and profile of the layers and their strain is investigated.
• A kinetic gas model is applied to predict the SiGe growth profile on Si-fins.

SiGe has been widely used as stressors in source/drain (S/D) regions of Metal–Oxide-Semiconductor Field Effect Transistor (MOSFET) to enhance the channel mobility. In this study, selectively grown Si1−xGex (0.33 ⩽ x ⩽ 0.35) with boron concentration of 1 × 1020 cm−3 was used to elevate the S/D regions on bulk FinFETs in 14 nm technology node. The epitaxial quality of SiGe layers, SiGe profile and the strain amount of the SiGe layers were investigated. In order to in-situ clean the Si-fins before SiGe epitaxy, a series of prebaking experiments at temperature ranging from 740 to 825 °C were performed. The results showed that the thermal budget needs to be limited to 780–800 °C in order to avoid any damage to the shape of Si-fins but to remove the native oxide which is essential for high epitaxial quality. In this study, a kinetic gas model was also applied to predict the SiGe growth profile on Si-fins with trapezoidal shape. The input parameters for the model include growth temperature, partial pressures of reactant gases and the chip layout. By knowing the epitaxial profile, the strain to the Si-fins exerted by SiGe layers can be calculated. This is important in understanding the carrier transport in the FinFETs. The other benefit of the modeling is that it provides a cost-effective alternative for epitaxy process development as the SiGe profile can be readily predicted for any chip layout in advance.