A manufacturable process integration approach for graphene devices

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

► Double gate graphene FETs with large area CVD graphene.
► Ultra-thin, high quality thermal SiO2 bottom gate dielectric and ALD Al2O3 top gate dielectric.
► Assessing the effect of Quantum capacitance and band bending on the GFET gate leakage currents.
► A CMOS compatible approach suitable for a range of graphene-based devices like hot electron transistors and photodetectors.